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A3987 DMOS Microstepping Driver with Translator
Features and Benefits
Low RDS(on) outputs Short-to-ground protection Shorted load protection Automatic current decay mode detection/selection Mixed and slow current decay modes Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection
Description
The A3987 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full, half, quarter, and sixteenth step modes, with output drive capability of 50 V and 1.5 A. The A3987 includes a fixed off-time current regulator, which has the ability to operate in slow or mixed decay modes. The translator is the key to the easy implementation of the A3987. Simply inputting one pulse on the step input drives the motor to take one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3987 interface is an ideal fit for applications where a complex microprocessor is unavailable or over-burdened. The A3987 chopping control automatically selects the current decay mode (slow or mixed). When a STEP signal occurs, the translator determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to slow decay. If the change is to a lower current, then the decay mode is set to 30.1% fast decay. This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation.
Continued on the next page...
Package: 24 pin TSSOP with exposed thermal pad (suffix LP)
Approximate scale
Typical Application Diagram
0.22 F VREG 10 F 5 k Microcontroller or Controller Logic ROSC STEP DIR SLEEP/RESET ENABLE MS1 MS2 REF VDD CP1
0.1 F X7R CP2 VCP 0.1 F X7R
VBB1
A3987
VBB2 OUT1A OUT1B SENSE1
100 F
OUT2A OUT2B SENSE2
3987DS, Rev.1
A3987
DMOS Microstepping Driver with Translator
protection. Special power-up sequencing is not required. The A3987 is supplied in a thin profile (1.2 mm maximum height) 24-lead TSSOP (suffix LP) with exposed thermal tab. The package is lead (Pb) free with 100% matte tin leadframe plating.
Description (continued) Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover current Selection Guide
Part Number
A3987SLP-T A3987SLPTR-T
Package
24-pin TSSOP with exposed thermal pad 24-pin TSSOP with exposed thermal pad
Packing
62 pieces / tube 3000 pieces / reel
Absolute Maximum Ratings
Characteristic Load Supply Voltage Output Current Logic Supply Voltage Logic Input Voltage Range VBBx to OUTx Sense Voltage Reference Voltage Nominal Operating Temperature Maximum Junction Temperature Storage Temperature VSENSE VREF TA TJ(max) Tstg Range S Symbol VBB IOUT VDD VIN Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. Notes Rating 50 1.5 7.0 -0.3 to VDD + 0.3 50 0.5 0 to 4 -20 to 85 150 -55 to 150 Units V A V V V V V C C C
Thermal Characteristics*
Characteristic Package Thermal Resistance *Additional thermal data available on the Allegro website.
Maximum Power Dissipation, PD(max)
5.5 5.0 4.5 4.0
Symbol RJA 2-layer PCB with 3.8
Notes 4-layer PCB based on JEDEC standard in.2 2 oz. copper each side
Rating 28 32
Units C/W C/W
Power Dissipation, PD (W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
(R
J
(R
J
A
=
28
C
A
=
/W
32
)
C
/W
)
20
40
60
80 100 120 Temperature (C)
140
160
180
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
2
A3987
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.22 F
0.1 F CP1 CP2 VCP
VREG
VDD
Regulator
Charge Pump
0.1 F
To VDD DAC VREG VCP PWM Latch Blanking Mixed Decay
DMOS Full Bridge 1
VBB1
OSC ROSC
OUT1A OUT1B
To VDD STEP DIR Translator SLEEP/RESET MS1 MS2 OUT2A ENABLE PWM Latch Blanking Mixed Decay OUT2B Gate Drive SENSE1 Control Logic
OCP
DMOS Full Bridge 2
VBB2
SENSE2 DAC Buffer REF
GND
GND
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
3
A3987
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS1 valid at TA = 25C, VBB = 50 V, unless noted otherwise Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage VBB VDD RDS(on) VF Operating During sleep mode Operating Source driver, IOUT = -1.5 A Sink driver, IOUT = 1.5 A Source diode, IF = -1.5 A Sink diode, IF = 1.5 A fPWM < 50 kHz Motor Supply Current IBB Operating, outputs disabled Sleep (idle) mode fPWM < 50 kHz Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Input Hysteresis Blank Time Fixed Offtime Reference Input Voltage Range Reference Input Current GM Error3 IREF VREF = 4 V, DAC = 37.5% Err tDT tRP tS VUVLO VUVHYS VDD rising VREF = 4 V, DAC = 70.31% VREF = 4 V, DAC = 100% Crossover Dead Time Reset Pulse Width Sleep Pulse Width UVLO Enable Threshold UVLO Hysteresis Continued on the next page... tBLANK tOFF fosc = 4 MHz ROSC tied to ground ROSC = 59 K VIN(1) VIN(0) IIN(1) IIN(0) VIN = VDD x 0.7 VIN = VDD x 0.3 VDD x 0.7 - -20 -20 150 0.7 15 23 0.8 -3 - - - 300 0.2 >2.5 2.35 0.05 - - <1.0 <1.0 - 1 25 30 - 0 - - - 650 - - 2.7 0.10 - VDD x 0.3 20 20 600 1.3 35 37 4 3 15 10 5 900 1 - 3 - V V A A mV ms ms ms V mA % % % ns s s V V IDD Outputs off Sleep mode 8 0 3.0 - - - - - - - - - - - - - 0.54 0.54 - - - - - - - - 50 50 5.5 0.6 0.6 1.2 1.2 4 2 20 12 10 100 V V V V V mA mA A mA mA A Symbol Test Conditions Min. Typ.2 Max. Units
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3987
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS1 (continued) valid at TA = 25C, VBB = 50 V, unless noted otherwise Characteristics Protection Circuitry Overcurrent Protection Threshold4 Overcurrent Blanking Thermal Shutdown Temperature Thermal Shutdown Hysteresis
1Negative
Symbol Test Conditions
Min.
Typ.2
Max.
Units
Iocpst tocp TTSD TTSDhys
2 1 - -
- 165 15
- 3 - -
A s C C
current is defined as coming out of (sourcing) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF / 8) - VSENSE ] / (VREF / 8). 4OCP is tested at T = 25C in a restricted range and guaranteed by characterization. A
tA
tB
STEP
tC MS1, MS2, RESET/SLEEP, or DIR tD
Time Duration STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram
Symbol tA tB tC tD
Typ. 1 1 200 200
Unit s s ns ns
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3987
DMOS Microstepping Driver with Translator
Table 1. Microstep Resolution Truth Table
MS1 L H L H MS2 L L H H Microstep Resolution Full step Half step Quarter step Sixteenth step Excitation Mode 2 phase 1-2 phase W1-2 phase 4W1-2 phase
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45; DIR = H
Full Step (#) Half Step (#) 1 1/4 Step (#) 1 1/16 Step (#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Phase 1 Current (% of ITRIP(max)) 0.00 9.38 18.75 29.69 37.50 46.88 56.25 64.06 70.31 76.56 82.81 87.50 92.19 95.31 98.44 100.00 100.00 100.00 98.44 95.31 92.19 87.50 82.81 76.56 70.31 64.06 56.25 46.88 37.50 29.69 18.75 9.38 0.00 Phase 2 Current (% of ITRIP(max)) 100.00 100.00 98.44 95.31 92.19 87.50 82.81 76.56 70.31 64.06 56.25 46.88 37.50 29.69 18.75 9.38 0.00 -9.38 -18.75 -29.69 -37.50 -46.88 -56.25 -64.06 -70.31 -76.56 -82.81 -87.50 -92.19 -95.31 -98.44 -100.00 -100.00 Step Angle () 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4 180.0 Full Step (#) Half Step (#) 5 1/4 Step (#) 9 1/16 Step (#) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 Phase 1 Current (% of ITRIP(max)) 0.00 -9.38 -18.75 -29.69 -37.50 -46.88 -56.25 -64.06 -70.31 -76.56 -82.81 -87.50 -92.19 -95.31 -98.44 -100.00 -100.00 -100.00 -98.44 -95.31 -92.19 -87.50 -82.81 -76.56 -70.31 -64.06 -56.25 -46.88 -37.50 -29.69 -18.75 -9.38 0.00 Phase 2 Current (% of ITRIP(max)) -100.00 -100.00 -98.44 -95.31 -92.19 -87.50 -82.81 -76.56 -70.31 -64.06 -56.25 -46.88 -37.50 -29.69 -18.75 -9.38 0.00 9.38 18.75 29.69 37.50 46.88 56.25 64.06 70.31 76.56 82.81 87.50 92.19 95.31 98.44 100.00 100.00 Step Angle () 180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4 360.0
2
10
1
2
3
3
6
11
4
12
3
5
7
13
6
14
2
4
7
4
8
15
8
16
5
9
1
1
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A3987
DMOS Microstepping Driver with Translator
STEP
100 70
STEP
100 70
Slow
Slow Mixed
Slow Mixed
Home Microstep Position
Home Microstep Position
-70 -100 100 70
Home Microstep Position
-70 -100 100 70
Slow Slow Mixed Mixed
Slow Mixed
Slow
Phase 2 IOUT2A DIR = H (%)
0
Slow
-70 -100
Phase 2 IOUT2B DIR = H (%)
0
-70 -100
Figure 2. Decay Mode for Full-Step Increments
STEP
100 94 70
Figure 3. Decay Modes for Half-Step Increments
-38 -70 -93 -100 100 93 70 38
Phase 2 IOUT2B DIR = H (%)
Slow Mixed Slow Mixed Slow Mixed
0
-38 -70 -93 -100
Figure 4. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Microstep Position
Phase 1 IOUT1A DIR = H (%)
38
Slow
0
Mixed
Slow
Mixed
Slow
Home Microstep Position
Phase 1 IOUT1A DIR = H (%)
Slow
0
Phase 1 IOUT1A DIR = H (%)
Mixed
0
7
A3987
DMOS Microstepping Driver with Translator
STEP
98100 95 92 88 83 77 70 64 56 47 38 29 19
Phase 1 IOUT1A DIR = H (%)
9 0 -9 -19 -29 -38 -47 -56 -64 -70 -77 -83 -88
Slow
Mixed
Slow
Mixed
-92 -95 -98 -100 98100 95 92 88 83 77 70 64 56 47 38 29 19
Phase 2 IOUT2B DIR = H (%)
9 0 -9 -19 -29 -38 -47 -56 -64 -70 -77 -83 -88
Slow Mixed Slow Mixed Slow
-92 -95 -98 -100
Figure 5. Decay Modes for Sixteenth-Step Increments
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Microstep Position
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A3987
DMOS Microstepping Driver with Translator
Functional Description
Device Operation The A3987 is a complete microstepping
motor driver with built-in translator for easy operation with a minimum of control lines. The A3987 is designed to operate bipolar stepper motors in full, half, quarter, and sixteenth step modes. The full bridges on the dual outputs are composed entirely of N-channel DMOS FETS, and the full bridge currents are regulated by fixed off-time, pulse width modulated (PWM) control circuitry. For each full bridge, the individual step currents are set by the combination of: a common external reference voltage, VREF ; an external current sense resistor, RSENSEx ; and the output voltage of an internal DAC that is controlled by the output of the translator. At power-up or reset, the translator sets the DACs and phase current polarity to the initial home state (see figures 2 through 5 for home state conditions), and also sets the current regulator for both output phases to mixed decay mode. When a command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence) and current polarity. The microstep resolution is set by inputs MS1 and MS2 (see in table 1 for state settings). If logic inputs are pulled up to VDD, it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs should an overvoltage event occur. If the new DAC output level is lower than the previous level, then the decay mode for that full bridge will be set to mixed decay. If the new DAC level is higher or equal to the previous level, then the decay mode for that full bridge will be slow decay. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform due to the motor BEMF.
Microstep Select (MS1 and MS2) Inputs MS1 and MS2
select the microstepping format (see table 1 for state settings). Changes to these inputs do not take effect until the next STEP command. It is good practice to use a pull-up resistor to VDD in order to limit input current should an external overvoltage occur. A minimum of 5 k is recommended.
Direction Input (DIR) The state of the DIR input determines
the direction of rotation of the motor. A logic change on the DIR pin will not take effect until the next STEP command is issued.
Internal PWM Current Control Each full bridge is
controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink FETs are enabled and current flows through the motor winding and the corresponding current sense resistor, RSENSEx. When the voltage across RSENSE equals the DAC output voltage, the current sense comparator resets the PWM latch, which turns off the source drivers (in slow decay mode) or the sink and source drivers (in fast or mixed decay modes). The maximum value of current limiting is set by the selection of RSENSE and the voltage at the REF input, with a transconductance function approximated by: ITRIP(max) = VREF / 8 x RSENSE . The DAC output reduces the VREF output to the current sense comparator in precise steps: ITRIP = (% ITRIP(max) / 100) x ITRIP(max) , (see table 2 for % ITRIP(max) at each step). Note: It is critical that the absolute maximum voltage rating (0.5 V) on the SENSE pins is not exceeded.
Low-Power Mode Select (SLEEP/RESET) An activelow control input used to minimize power consumption when the A3987 is not in use. This disables much of the internal circuitry including the output FETs and internal regulator. A logic high allows normal device operation and power-up in the home state. When coming out of sleep mode, a 1 ms delay is required before issuing a STEP command, to allow the internal regulator to stabilize. The outputs can also be reset to the home state without entering sleep mode. To do so, pulse this input low for a duration between tRP(min) and tRP(max).
Fixed Off-Time The internal PWM current control circuitry
uses a 4 MHz master oscillator to control the duration of time that the drivers remain off. The fixed off-time, tOFF , is determined by the selection of an external resistor connected from the ROSC timing terminal to VDD. If the ROSC terminal is tied directly to GND, tOFF defaults to 25 s. The off-time is approximated by: tOFF ROSC / 1.981 x 109 The master oscillator period is used to derive PWM off-time, dead time, and blanking time.
Step Input (STEP) A low-to-high transition on the STEP
input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current control circuitry. The comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of 9
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A3987
DMOS Microstepping Driver with Translator
the internal body diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK , is internally set to approximately 1 s.
decay portion, tFD , the device switches to slow decay mode for the remainder of the fixed off-time period.
Synchronous Rectification When a PWM off-cycle is
triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3987 synchronous rectification feature turns on the appropriate FETs during current decay, effectively shorting out the body diodes in the low RDS(on) driver. This lowers power dissipation significantly, and can eliminate the need for external Schottky diodes for many applications. To prevent reversal of load current, synchronous rectification is turned off when a zero current level is detected.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than VBBx to drive the source FET gates. A 0.1 F ceramic capacitor is required between CP1 and CP2 for pumping purposes. A 0.1F ceramic capacitor is required between VCP and the VBB terminals to act as a reservoir to operate the high-side FETs.
Internal Regulator (VREG) The VREG terminal should be decoupled with a 0.22 F capacitor to ground. This internally generated voltage is used to operate the sink FET outputs. VREG is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE) This input activates all of the FET outputs. When logic high, the outputs are disabled, and when logic low, the outputs are enabled. Inputs to the translator (STEP, DIR, MS1, and MS2) are always active, except in Sleep mode, regardless of the ENABLE input state. Shutdown In the event of a fault (either excessive junction
temperature, or low voltage on VCP), the outputs of the device are disabled until the fault condition is removed. At power-up, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the home state.
Short-to-Ground Should a motor winding short to ground,
the current through the short will rise until the overcurrent threshold, ICOPST , a minimum of 2 A, is exceeded. The driver turns off after a short propagation delay and latches the fault. The device will remain disabled until the SLEEP/RESET input goes high or VDD power is removed. As shown in figure 6, a short-to-ground produces a single overcurrent event.
Shorted Load During a shorted load event, the current path is
through the sense resistor. During this fault condition the device will be protected, however, the fault will not be latched. When the full bridge turns on, the current will rise and exceed the overcurrent threshold. After the blank time,tBLANK , of approximatly 1 s, the driver will look at the voltage on the SENSEx pin. The voltage on the SENSEx pin will be larger than the voltage set by the REF pin, and the full bridge will turn off for the time set by the ROSC pin. Figure 7 shows a shorted load condition with an off-time of 30 s.
Mixed Decay Operation The full bridges can operate in
mixed decay mode when set by the step sequence (see figures 3 through 5). As the trip point is reached, the device goes into fast decay mode for 30.1% of the fixed off-time, tOFF. After this fast
Fault latched
toff = 30 s
2 A / div. 500 ns / div.
2 A / div. 5 s / div.
Figure 6. Short-to-ground event
Figure 7. Short-to-load event
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10
A3987
DMOS Microstepping Driver with Translator
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3987 must be soldered directly onto the board. On the underside of the A3987 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A3987, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout, shown in figure 8, illustrates how to create a star ground under the device, to serve both as a low impedance ground point and thermal path. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components.
The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in figure 8, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits.
A3987
Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.)
PCB Thermal Vias
OUT1A GND
OUT1B VIN
OUT1A RS1 1
OUT1B
VIN
SENSE1 OUT1A NC MS1
VBB1 MS2 OUT1B
RS1 U1 CCP CVCP
A3987
PAD
CP2 CP1 VCP GND ROSC
CCP CVCP ROSC CIN2 CREG
DIR STEP GND REF
CREF ROSC
CREF
ENABLE VDD OUT2A SENSE2
SLEEP/RESET VREG OUT2B VBB2
CIN2 CVDD
RS2
CIN1
RS2 CREG CIN1
VREF
VREF OUT2A OUT2B
OUT2A
CVDD
OUT2B
Figure 8. Printed circuit board layout with typical application circuit, shown at right. The copper area directly under the A3987 (U1) is soldered to the exposed thermal pad on the underside of the device.
The thermal vias serve also as electrical vias, connecting it to the ground plane on the other side of the PCB , so the two copper areas together form the star ground.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
11
A3987
DMOS Microstepping Driver with Translator
Device Pin-out Diagrams
SENSE1 1 OUT1A 2 NC 3 MS1 4 DIR 5 STEP 6 GND 7 REF 8 ENABLE 9 VDD 10 OUT2A 11 SENSE2 12 PAD
24 VBB1 23 MS2 22 OUT1B 21 CP2 20 CP1 19 VCP 18 GND 17 ROSC 16 SLEEP/RESET 15 VREG 14 OUT2B 13 VBB2
Terminal List Table Number
1 2 3 4 5 6 7, 18 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 -
Name
SENSE1 OUT1A NC MS1 DIR STEP GND REF ENABLE VDD OUT2A SENSE2 VBB2 OUT2B VREG SLEEP/RESET ROSC VCP CP1 CP2 OUT1B MS2 VBB1 PAD
Pin Description
Sense resistor terminal for Full Bridge 1 DMOS Full Bridge 1, output A No connection Logic input Logic input Logic input Ground terminals Gm reference input Logic input Logic supply DMOS Full Bridge 2, output A Sense resistor terminal for Full Bridge 2 Load supply DMOS Full Bridge 2, output B Internal regulator Logic input Oscillator input Reservoir capacitor terminal Charge pump capacitor terminal Charge pump capacitor terminal DMOS Full Bridge 1, output B Logic input Load supply Exposed thermal pad for enhanced thermal dissipation.
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12
A3987
DMOS Microstepping Driver with Translator
Package LP, 24 Pin TSSOP with Exposed Thermal Pad
24 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MO-153 ADT) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 24X 0.10 [.004] C 24X 0.30 .012 0.19 .007 0.10 [.004] M C A B
7.9 7.7
.311 .303
A B
8 0 0.20 .008 0.09 .004
B
4.5 4.3
.177 .169 6.6 6.2 .260 .244
0.75 .030 0.45 .018 1 .039 REF
A
1
2 0.25 .010 SEATING PLANE 0.65 .026 1.20 .047 MAX 0.15 .006 0.00 .000 0.65 .026 NOM C SEATING PLANE GAUGE PLANE
0.45 .018 NOM
2X 0.20 .008 MIN C
3 .118 NOM
5.9 .232 NOM
1.85 .073 NOM
4.32 .170 NOM
22X 0.20 .008 MIN
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright (c)2006, 2007, Allegro MicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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